Semiconductor device and manufacturing method thereof

ABSTRACT

A transistor of a semiconductor device has an increased driving capacity. The semiconductor device has a first gate insulation film formed by a selective oxidation, a second gate insulation film formed by thermal oxidation and a gate electrode formed across the first and the second gate insulation films. The second gate insulation film is composed of a thicker gate insulation film and a thinner gate insulation film.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] This invention relates to a semiconductor device and itsmanufacturing method, specifically to a high voltage MOS (Metal OxideSemiconductor) transistor with an increased driving capacity for a levelshifter used in an LCD (Liquid Crystal Display) driver, an EL (ElectroLuminescence) driver and the like.

[0003] 2. Description of the Related Art

[0004] A semiconductor device according to a conventional art will beexplained hereinafter referring to a cross-sectional view of an LOCOS(Local Oxidation of Silicon) offset type high voltage MOS transistorshown in FIG. 9.

[0005] A gate electrode 53 is formed on a first gate insulation film 52Aand a second gate insulation film 52B on a semiconductor layer 51 of afirst conductivity (P-type in this example), as shown in FIG. 9. An N+source region 54 is formed adjacent one edge of the gate electrode 53.An N− drain region 56 is formed facing to the N+ source region 54 acrossa channel region 55. And an N+ drain region 57 is formed within the N−drain region 56 and apart from the other edge of the gate electrode 53.A numeral 58 refers to a device isolation film.

[0006] The second gate insulation film 52B is thicker than the gateinsulating film of a normal voltage (e.g. 10V) MOS transistor. That isto say, for instance, the gate insulation film of the high voltage MOStransistor is about 120 nm thick while that of the normal voltage MOStransistor is about 15 nm thick.

[0007] A LOCOS insulation film (the second gate insulation film 52B) isformed on the N− drain region in order to increase a maximum voltageapplicable to the device by relieving an electric field concentration inthat area.

[0008] A weak inversion leakage current increases when the gateinsulation film becomes thicker. Therefore raising a threshold voltageby forming an ion-implanted layer in the channel region is necessary inorder to suppress the leakage current.

[0009] However, on the other hand, when the threshold voltage is raised,a driving capacity of the transistor is reduced.

SUMMARY OF THE INVENTION

[0010] This invention is directed to a semiconductor device withimproved driving capacity and its manufacturing method.

[0011] The semiconductor device of this invention has a gate electrodeformed on a gate insulation film on a semiconductor layer, and sourceand drain regions formed adjacent the gate electrode, while the gateinsulation film has three or more different thicknesses.

[0012] The semiconductor device of this invention has a first gateinsulation film formed by a selective oxidation and second gateinsulation film formed by a thermal oxidation on the semiconductorlayer. The gate electrode is formed across the first and the second gateinsulation film, wherein the second gate insulation film consists of aplurality of gate insulation films of different thicknesses.

[0013] The second gate insulation film consists of a thicker second gateinsulation film and a thinner second gate insulation film, and the firstgate insulation film is thicker than the thicker second gate insulationfilm.

[0014] In a manufacturing process of the semiconductor device of thisinvention, which has the first gate insulation film formed by aselective oxidation and the second gate insulation film formed by athermal oxidation of the semiconductor layer and the gate electrodeformed across the first and the second gate insulation films, the secondgate insulation film is formed in the following steps. The thickersecond gate insulation film is formed on the semiconductor layer. Apredetermined area of the thicker second gate insulation film isremoved. Then, the thinner second gate insulation film is formedbordering on the thicker second gate insulation film.

[0015] In a manufacturing method of the semiconductor device of thisinvention, the second gate insulation film can be formed after the firstgate insulation film is formed.

[0016] In a manufacturing method of the semiconductor device of thisinvention, the second gate insulation film can be formed before thefirst gate insulation film is formed.

[0017] A manufacturing method of the semiconductor device of thisinvention has a process to form a LOCOS insulation film by selectiveoxidation of a semiconductor layer with a mask of an oxidation resistantfilm formed on the semiconductor layer, a process to form a thicker gateinsulation film bordering on the LOCOS insulation film after removingthe oxidation resistant film, a process to form a thinner gateinsulation film bordering on the thicker gate insulation film by thermaloxidation after removing a predetermined portion of the thicker gateinsulation film, a process to form a gate electrode across the thinnergate insulation film, thicker gate insulation film and the LOCOSinsulation film and a process to form source and drain regions adjacentthe gate electrode.

[0018] A LOCOS insulation film is formed by selective oxidation of thesemiconductor layer using an oxidation resistant film as a mask, afterforming an insulation film or an insulation film and a polysilicon filmon the semiconductor layer.

BRIEF DESCRIPTION OF THE DRAWINGS

[0019]FIG. 1 is a cross-sectional view showing a device intermediateaccording to a manufacturing method of a semiconductor device of anembodiment of this invention.

[0020]FIG. 2 is a cross-sectional view showing a device intermediateaccording to the manufacturing method of the semiconductor device of theembodiment, following the step of FIG. 1.

[0021]FIG. 3 is a cross-sectional view showing a device intermediateaccording to the manufacturing method of the semiconductor device of theembodiment, following the step of FIG. 2.

[0022]FIG. 4 is a cross-sectional view showing a device intermediateaccording to the manufacturing method of the semiconductor device of theembodiment, following the step of FIG. 3.

[0023]FIG. 5 is a cross-sectional view showing a device intermediateaccording to the manufacturing method of the semiconductor device of theembodiment, following the step of FIG. 4.

[0024]FIG. 6 is a cross-sectional view showing a device intermediateaccording to the manufacturing method of the semiconductor device of theembodiment, following the step of FIG. 5.

[0025]FIG. 7 is a cross-sectional view showing a device intermediateaccording to the manufacturing method of the semiconductor device of theembodiment, following the step of FIG. 6.

[0026]FIG. 8 is a cross-sectional view showing a device intermediateaccording to the manufacturing method of the semiconductor device of theembodiment, following the step of FIG. 7.

[0027]FIG. 9 is a cross-sectional view showing a conventionalsemiconductor device.

DETAILED DESCRIPTION OF THE INVENTION

[0028] A semiconductor device and its manufacturing method of anembodiment of this invention, applied to an N-channel MOS transistor fora level shifter, will be explained referring to the drawings.

[0029] A manufacturing method of the semiconductor device will beexplained hereafter.

[0030] As shown in FIG. 1, a P-type semiconductor layer 2 is formed on asemiconductor (Si) substrate 1 of a first conductivity, e.g. P-type by aboron-ion implantation of 1×10¹³/cm² at an acceleration voltage of 80KeV and a diffusion of the boron ions at about 1200° C. for 8 hrs in aN₂ atmosphere.

[0031] As shown in FIG. 2, about 15 nm of an insulation film 3 and about50 nm of a polysilicon film 4 are formed on an entire surface of thesubstrate, and then N-type impurities, e.g. 7×10¹²/cm² of phosphorousions, are implanted at an acceleration voltage of 140 KeV with a mask ofphoto-resist 5 formed on the polysilicon film 4. With this, an ionimplanted layer 6 is formed in a region to make the drain of theN-channel MOS transistor for the level shifter. The insulation film 3and the polysilicon film 4 are so called pad oxide film and padpolysilicon film for the LOCOS insulation film formation, which will bedescribed later.

[0032] Next as shown in FIG. 3, a device isolation film 8A and a firstgate insulation film 8B, both made of the LOCOS insulation film, areformed by a selective oxidation of the substrate with a mask of asilicon nitride film 7 formed on the polysilicon film 4. The impuritiesin the ion-implanted layer 6 are diffused to form a low impurityconcentration drain region (N− layer) 9 during the selective oxidation.The LOCOS insulation film may also be formed using only the pad oxidefilm, rather than using both the pad polysilicon film and the pad oxidefilm.

[0033] Then about 120 nm of thicker gate insulation film 10 (a part of asecond gate insulation film) is formed by a pyrolytic oxidation of thesurface of the substrate as shown in FIG. 4.

[0034] As shown in FIG. 5, a photo-resist film 11 is formed on the firstgate insulation film 8B and the thicker gate insulation film 10. Then apart of the insulation film 10, which is not covered by the photo-resistfilm 11 is removed, leaving thicker gate insulation film 10A adjacentthe first gate insulation film 8B.

[0035] And as shown in FIG. 6, a thinner gate insulation film 12 (theother part of the second gate insulation film) of 15 nm in thickness isformed adjacent the thicker gate insulation film 10A by a pyrolyticoxidation of the substrate at about 850° C. followed by a thermaltreatment at 900° C. for 10 min, after removing the photo-resist film11. The surface layer of the substrate under the gate insulation film10A is oxidized to increase the thickness of the gate insulation film10A a little during this process.

[0036] P-type impurities for threshold voltage (the voltage of the onsetof an inversion layer formation) control, e.g. 1×10¹²/cm² of boron ions,are implanted into a portion under the region to form a gate electrode(under the thinner gate insulation film 12) at an acceleration voltageof 35 KeV with a mask of photo-resist film (not shown in the figure).

[0037] In this invention as described above, the ion implantation forthreshold control is made only to the portion under the thinner gateinsulation film 12 and not to a portion under the thicker gateinsulation film 10A. Therefore an impurity concentration in the portionof the P-type semiconductor layer 2 under the thicker gate insulationfilm remains low. Because of this low impurity concentration under thethicker gate insulation film, the maximum drain voltage applicable tothe device can be significantly higher than that of the conventionalstructure. Furthermore, the thicker gate insulation film 10A canwithstand a high voltage applied at the gate electrode and, thus,further contributes to a higher maximum voltage applicable to thedevice.

[0038] The portion of the semiconductor layer 2 under the thinner gateinsulating film 12 has a low threshold voltage because of the thinnerinsulation film and, thus, provides a large driving capacity of thedevice. The level of the threshold voltage is adjusted by theimplantation of P-type impurities.

[0039] The ion implantation for threshold control can be done with aself aligned method, i.e. not using the photo-resist, taking advantageof a difference in thickness between the gate insulation films 10A and12. Furthermore, the ion implantation for threshold control can be madeto both portions under the gate insulation films 10A and 12. In thiscase, an impurity concentration profile difference due to the differencein thickness between the gate insulation films 10A and 12 assures a highmaximum drain voltage in the portion under the thicker gate insulationfilm 10A and a threshold voltage controlled at a low level in theportion under the thinner gate insulation film 12.

[0040] Then, as shown in FIG. 7, a phosphorous-treated polysilicon filmhaving a thickness of about 10 nm and a silicide film (tungstensilicide, WSix, film in this embodiment) having a thickness of about 15nm are formed on the entire surface of the substrate in this order.These two films are patterned using a mask of photoresist film (notshown in the figure) to form a gate electrode 15 consisting of thetungsten silicide 14 stacked on the polysilicon film 13. Portions of thethinner gate insulation film 12, which is not covered by the gateelectrode 15, are, then, removed.

[0041] Next as shown in FIG. 8, a high impurity concentration sourceregion (N+ layer) 16 located adjacent on edge of the gate electrode 15and a high impurity concentration drain region (N+ layer) 16 located inan area apart from the gate electrode 15 through the first gateinsulation film 8B are formed by implanting N-type impurities, e.g.5×10¹⁵/cm² of arsenic ions, at an acceleration voltage of 70 KeV usingthe device isolation film 8A, the first gate insulation film 8B and thegate electrode 15 as a mask.

[0042] Furthermore, an interlayer insulation film 17, which is a stackedlayer of NSG (Non-doped Silicate Glass) film and BPSG (Boro-PhosphoSilicate Glass) film in the embodiment, is formed on the entire surfacefollowed by a formation of a metal interconnect (Al film, Al—Si film orAl—Si—Cu film for example) 18, which contacts with the source and thedrain regions 16 through contact holes formed in the interlayerinsulation film 17.

[0043] A passivation film (not shown in the figure) is formed on theentire surface to complete the semiconductor device of this invention.

[0044] In the high voltage MOS transistor of the embodiment shown inFIG. 8, to which a high voltage is applied only at a drain, a highmaximum voltage applicable to the device is secured in a portion of athicker gate insulation film 10A by forming a drain side gate insulationfilm with the thicker gate insulation film 10A, while the thresholdvoltage is controlled at a low level in a portion of a thinner gateinsulation film 12.

[0045] Including a LOCOS insulation film 8B which composes a LOCOSoffset structure, the gate insulation films are made of three differentfilms, i.e. the thicker gate insulation film 10A, thinner gateinsulation film 12 and the LOCOS insulation film 8B. These three filmeach have different thickness and contribute to relieving electric fieldconcentration.

[0046] In this embodiment, as described above, a first gate insulationfilm 8B made of the LOCOS insulation film is formed first, and thickergate insulation film 10A (a part of the second gate insulation film) isformed adjacent the first gate insulation film 8B, and a portion of thethicker second gate insulation film 10A is removed, and then the thinnersecond gate insulation film 12 (the other part of the second gateinsulation film) is formed bordering on the thicker second gateinsulation film. The order to form each of the insulation films 8B, 10Aand 12 is not limited to the order described above, but there are somevariations.

[0047] That is, the second gate insulation film can be formed before thefirst gate insulation film, the order to form two films 10A and 10Bforming the second gate insulation film can be reversed, the first gateinsulation film 8B can be formed between the formations of the two films10A and 10B and so on.

[0048] Additionally, this invention can be applied to a P-channel MOStransistor for a level shifter, although an N-channel MOS transistor fora level shifter is introduced in the embodiment.

[0049] Furthermore, this invention is not only applied to an MOStransistor for a level shifter, but also can be applied to an MOStransistor to which a high maximum drain voltage is required in general.

[0050] Moreover, this invention is not only applied to a LOCOS offsettype semiconductor device, but also can applied to other semiconductordevice which secures a high maximum drain voltage while improving adriving capacity of a transistor taking advantage of the difference inthickness of a gate insulation film formed by thermal oxidation.

[0051] According to this invention, by forming the gate insulation filmwith two or more thicknesses, the electric field concentration can berelieved in comparison to the conventional device.

[0052] By having a thicker gate insulation film and a thinner gateinsulation film disposed on the semiconductor layer, a high maximumdrain voltage can be applied to the device because of the thicker gateinsulation film while the threshold voltage is controlled at a low levelin the portion of the semiconductor layer under the thinner gateinsulation film, leading to an improved driving capacity of thetransistor.

[0053] The above is a detailed description of a particular embodiment ofthe invention which is not intended to limit the invention to theembodiment described. It is recognized that modifications within thescope of the invention will occur to a person skilled in the art. Suchmodifications and equivalents of the invention are intended forinclusion within the scope of this invention.

What is claimed is:
 1. A semiconductor device comprising: asemiconductor layer; a gate insulation film formed on the semiconductorlayer and comprising three insulation films each having a differentthickness; a gate electrode formed on the gate insulation film; and asource region and a drain region each formed adjacent the gateelectrode.
 2. A semiconductor device comprising: a semiconductor layer;a first gate insulation film formed by selective oxidation; a secondgate insulation film formed by thermal oxidation and comprising twoinsulation films each having a different thickness; and a gate electrodeformed across the first and second gate insulation films.
 3. Thesemiconductor device of claim 2, wherein the first gate insulation filmis thicker than any of the insulation films of the second gateinsulation film.
 4. A manufacturing method of a semiconductor devicecomprising: providing a substrate forming a first gate insulation filmon a semiconductor layer of the substrate by selective oxidation;forming a second gate insulation film on the semiconductor layer bythermal oxidation, the second gate insulation film comprising twoinsulation films each having a different thickness; and forming a gateelectrode across the first and the second gate insulation films.
 5. Themanufacturing method of claim 4, wherein the forming of the second gateinsulation film comprises forming a first insulation film of a firstthickness, removing the first insulation film from a predeterminedportion of the substrate and forming a second insulation film of asecond thickness in a portion adjacent the remaining first insulationfilm, the second insulation film being thinner than the first insulationfilm.
 6. The manufacturing method of a semiconductor device of claim 4,wherein the second gate insulation film is formed after the first gateinsulation film is formed.
 7. The manufacturing method of asemiconductor device of claim 4, wherein the second gate insulation filmis formed before the first gate insulation film is formed.
 8. Amanufacturing method of a semiconductor device comprising: providing asubstrate; forming a LOCOS insulation film at a predetermined region ofa semiconductor layer of the substrate by selective oxidation using anoxidation resistant film as a mask; forming a first gate insulation filmof a first thickness adjacent the LOCOS insulation film by thermallyoxidizing the semiconductor layer after removing the oxidation resistantfilm; removing a portion of the first gate insulation film; forming asecond gate insulation film of a second thickness at a portion of thesubstrate adjacent the remaining first gate insulation film by thermallyoxidizing the semiconductor layer, the second gate insulating film beingthinner than the first gate insulating film; a process to form a gateelectrode across the gate insulation film of the first thickness, thegate insulation film of the second thickness and the LOCOS gateinsulation film; and forming a source region and a drain region eachadjacent the gate electrode.
 9. The manufacturing method of asemiconductor device of claim 8, further comprising forming a padinsulation film or a pad insulation film and a pad polysilicon film onthe semiconductor layer before forming the LOCOS insulation film.